We have a number of successful implementation of designs onto FPGAs, Gate Arrays, Standard Cell, and transistor level full custom ASICs and complex SoCs. Standing by our clients, we have worked alongside with large foundries and have successfully transformed many designs from RTL to GDSII, performing all physical verification checks including timing, power, logic equivalency, layout versus schematic, on chip variation, cross talk, etc. The seamless integration that we ensure between physical design and design functions, results in a manageable, high performance, low risk and efficient physical implementation.

Aided by the expertise of our in-house methodology developed with the aid of industry standard toolsets and technologies, Graphene provides complete support to our customer's methodology in areas of:

• RTL to GDSII (With Package Design & Tested Samples)
• Netlist to GDSII (With Package Design & Tested Samples)
• GDSII to Tested Engineering Samples
• Technology Migration
• Foundry Migration
• Backend Flow & Methodology development

Team Skills & Expertise

Graphene PD team comes with varied skills and expertise that covers entire chip implementation cycle.

Tools:

• P&R Design flow: Expertise on ICC, EDI, Olympus toolsets. When needed, team has also ramped up fast on Atoptech as well as supported legacy flows based on MAGMA
• STA: PTSI, ETS, Goldtime and some of the customer specific tools
• Power: VoltageStorm (now Voltus), Redhawk
• Physical Verification: Calibre, Hercules and some of the customer specific tools
• Scripting: Team comes with strength and attitude for automation. Strong in TCL (for ICC, EDI, MAGMA etc.), Perl, Make, SKILL and other utilities
• Analog layout: Virtuoso XL, HSPICE, Spectre

Technology Node & Flow Expertise:

While the team comes with a tapeout experience on older nodes viz. 40nm, 65nm and above, most projects handled recently have been on 16nm, 14nm and 28nm. However, following is the spread of our technology expertise:

• UPF/CPF based advanced low power flow
• MMMC/AOCV/POCV based High performance Flow
• Flat/Hierarhical, Abutted/Channel based module level design implementation flows
• Flipchip/ Wirebond implementation

Target application:

The team has experience working on following application types:

• Processors: ARM Cortex A/ R series
• TV, DSP and Multimedia
• Modems
• Large telecom, memory SOCs consisting of prevailing standard protocols like DDR/ PCIe/ Sata/ USB/ CSI-DSI etc.
• Testchips: Team has recently taped out testchips at 16nm with an aggressive schedule

Deep submicron technologies demand complex designs which cannot be created without good methodology at all stages of the design cycle. This efficiency is imperative for a quick turnaround and the advantage of “first time success” that leads to faster time to market, coupled with high reliability and yield.

Inevitably, first time success can only be ensured when perfect testing processes are in place. Graphene’s expertise in handling various testing processes and our deep experience in the design testing space, give us the advantage of flawless testing for each of the designs that our clients get.

Our DFT services include:

• Scan insertion
• BIST (MBIST and LBIST) insertion
• JTAG insertion
• Test Pattern generation and simulation
• Coverage enhancement/ improvement

Using standard tool sets that assimilate the client’s methodology we provide testing strengths by:

• Experience in design flow using the standard toolset
• Expertise in handling various DFT features like Scan, BIST, and JTAG etc.
• Good integration with physical design flows to reduce iterations
• A robust methodology based on available toolset
• Thorough audits and reviews at different stages in the design flow ensuring quality deliverables
• Processes that ensure proactive and close interaction with client

Our biggest advantage is that the designers spend quality time at the planning stage, making the methodology fool-proof as the operation progresses. The customer is kept aware of the fault coverage pre- and post- DFT feature insertion and his concurrence is sought before the designer can take the design through the actual DFT feature insertion process.

In our design methodology equal emphasis is placed on each step required in inserting DFT features in the design. Close assessment and tracking and precise documentation of every step ensures a smooth and appropriate insertion, with regular reviews scheduled at the following stages:

• Kickoff
• Test Plan
• Post-DFT insertion

Our DFT capabilities include:

• Internal Quality Checks on the design inputs and library inputs
• Developing the necessary automation utilities/scripts based on actual inputs
• Test Plan provides entire information about the Test Methodology depending upon client requirements.
• DFT checks at Sub-chip level, Scan-Insertion at Sub-chip level, MBIST insertion at Sub-chip level, Formal equivalence check, Fault-Coverage analysis at Sub-chip level, ATPG and MBIST pattern verification at Sub-chip level, Top-Level (Boundary Scan) creation, Integration of all Sub-chips and DFT violation check.
• Top-Level ATPG fault-coverage analysis and ATPG and MBIST pattern generation and Verification
• Interacting with Physic Design team for DFT design closure
• Performing gate level simulations with delays annotated
• Final Tester format generation and Verification with post route netlist.

Languages and Tools

Graphene DFT services are offered around industry standard tools from Synopsys & Mentor Graphics etc. Automation is achieved through MAKE, TCL, PERL etc.

Analog and Mixed signal design encompass two vital portions of VLSI designs – Digital and Analog blocks.

Graphene has developed a unique design environment for high-quality analog and digital design in a structured way, resulting in a high reliability and high first-time-right success rate. Our in- house methodologies offer fast and accurate full chip-level mixed-signal simulation coverage with EDA simulators such as Spectre , Ultraism , AMS +Ultrasim and System Verilog etc.

At Graphene, the deep domain expertise of our Analog and Custom layout team has ensured an impressive list of extremely satisfied clients. Their expertise also extends to consulting on custom layout aspects of these and any other design requirement.

The team has experience on technology nodes ranging from 130nm all the way to 14nm having supported designs in different application domains.

The strengths that our Analog and Mix signal design team brings you are:

• Reduction in:
  • the bill-of-material costs of your product
  • test and assembly costs
  • The size and weight
  • power consumption
• Protection of customer IP
• Increased performance and reliability

Our capabilities lie in the following areas:

• Mixed Signal / Analog Layout and Validation of Layout with post layout simulations
• Mixed Signal Circuit Design
• Characterization
• Independent Signal Integrity Analysis

Graphene’s analog team offers building blocks across the following technology nodes:

• Technology nodes - 14nm/ 16nm/ 28nm / 45nm
• Building blocks: OPAMP, Band Gap, Crystal Oscillators, LDOs, GPIO and High Speed IOs - DDR2, HSTL, PECL, LVDS
• Other complex blocks: SERDES, CML Drivers, ADC, RF Transceiver, PLL, OPAMP, Band gap, LDO, DC-DC converters
• Independent Signal Integrity Analysis
• Value add with CAD support by developing “point automation” tools
• Develop independent IBIS models.